/**************************************************************************** 
* 
* Copyright (c) 2022  C*Core -   All Rights Reserved  
* 
* THIS SOFTWARE IS DISTRIBUTED "AS IS," AND ALL WARRANTIES ARE DISCLAIMED, 
* INCLUDING MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
* 
* PROJECT     : CCFC2011BC           
* DESCRIPTION : mpu demo code
* HISTORY     : 2022
* @file     mpu_demo.h
* @version  3.0
* @date     2022-10-27
* @brief    Initial version.
*
*****************************************************************************/

#ifndef MPU_DEMO_H_
#define MPU_DEMO_H_
#include "CCFC2011BC.h"
#include "mpu_lld.h"

/* 
 * Demo switch***************************************************/
#define MPU_BASE_FUNC_DEMO1_SW      1U
#define MPU_BASE_FUNC_DEMO2_SW      0U
#define MPU_BASE_FUNC_DEMO3_SW      0U
#define MPU_BASE_FUNC_DEMO4_SW      0U
#define MPU_PID_DEMO1_SW            0U
#define MPU_PID_DEMO2_SW            0U
#define MPU_PID_DEMO3_SW            0U
#define MPU_OVERLAP_DEMO1_SW        0U
#define MPU_OVERLAP_DEMO2_SW        0U
#define MPU_OVERLAP_DEMO3_SW        0U

/* 
 * ADDR***************************************************/
#define CFLASH0_ADDR_S  (0x00000000u)
#define CFLASH0_ADDR_E  (0x0007FFFFu)
#define CFLASH1_ADDR_S  (0x00080000u)
#define CFLASH1_ADDR_E  (0x000FFFFFu)
#define CFLASH2_ADDR_S  (0x00100000u)
#define CFLASH2_ADDR_E  (0x0017FFFFu)

#define SRAM0_ADDR_S    (0x40000000u)
#define SRAM0_ADDR_E    (0x4000FFFFu)
#define SRAM1_ADDR_S    (0x40010000u)
#define SRAM1_ADDR_E    (0x40017FFFu)

#define SIUL_ADDR_S     (0xC3F90000u)
#define SIUL_ADDR_E     (0xC3F93FFFu)

#define LINFLEX0_ADDR_S (0xFFE40000u)
#define LINFLEX0_ADDR_E (0xFFE43FFFu)
#define LINFLEX1_ADDR_S (0xFFE44000u)
#define LINFLEX1_ADDR_E (0xFFE47FFFu)
#define LINFLEX2_ADDR_S (0xFFE48000u)
#define LINFLEX2_ADDR_E (0xFFE4BFFFu)
#define LINFLEX3_ADDR_S (0xFFE4C000u)
#define LINFLEX3_ADDR_E (0xFFE4FFFFu)
#define LINFLEX4_ADDR_S (0xFFE50000u)
#define LINFLEX4_ADDR_E (0xFFE53FFFu)
#define LINFLEX5_ADDR_S (0xFFE54000u)
#define LINFLEX5_ADDR_E (0xFFE57FFFu)
#define LINFLEX6_ADDR_S (0xFFE58000u)
#define LINFLEX6_ADDR_E (0xFFE5BFFFu)
#define LINFLEX7_ADDR_S (0xFFE5C000u)
#define LINFLEX7_ADDR_E (0xFFE5FFFFu)

#define MPU_ADDR_S      (0xFFF10000u)
#define MPU_ADDR_E      (0xFFF13FFFu)

#define BAM_ADDR_S      (0xFFFFC000u)
#define BAM_ADDR_E1     (0xFFFFC800u)
#define BAM_ADDR_E      (0xFFFFFFFFu)

#define MC_RGM_S        (0xC3FE4000u)
#define MC_RGM_E        (0xC3FE7FFFu)

/************************************************************************
 *    Functional declarations
 ************************************************************************/
extern void MPU_Test_Demo(void);

#endif  /* MPU_DEMO_H_ */
